Layout Interview Questions BY Poornima Jenaras -Bangalore-VLSI Designers

**THIS SERIES DONATED BY Poornima Jenaras in our ORKUT GROUP Bangalore-VLSI Designers **

1) According to Clein, what has been one of the main reasons why CAD tools have failed to be successful among IC layout engineers?

2) With respect to CAD tools, what are some of the advantanges and disadvantages to being a small IC design house?

advantages:good integration of tools and service cut off their time wasted on tools
disadvantages:too expensive

3) What is an IC design flow? Why do IC design teams operate within the constraints of design flows?

Constrain in a flow in order to integrating different part of a system and with expected results

4) Why are PMOS transistor networks generally used to produce high (i.e. 1) signals, while NMOS networks are used to product low (0) signals?

PMOS is used to drive 'high' because of the thresholdvoltage-effect The same is true for NMOS to drive 'low'.

A NMOS device cant drive a full '1' and PMOS cant drive full '0'Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing

5) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean?

The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)
If given only one number it's the width combined with a default length


6) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates) usually limited to four?

To limit the height of the stack.

As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be.

7) What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero?

8) What is a transmission gate, and what is it used for typically? Why
are transmission gates made with both PMOS and NMOS transistors?

9) What are the major factors that determine the speed that a logic signal
propagates from the input of one gate to the input of the next driven gate
in the signal's path?

10) What are some of the major techniques that are usually considered when
one wants to speed up the propagation speed of a signal?

11) What is the difference between a mask layer and a drawn layer in an
IC layout? Why do layout designers usually only specify drawn layers?

12) In an IC layout, what is a polygon and what is a path? What are the
advantages and disadvantages of each?

A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it's off grid with 45 degree angle. Polygon is always on-grid, unless it's a copy and flip. However, polygon is hard to edit and work with.

13) What is the difference between a contact and a via? What is a "stacked" via process?

Via: a contact between two conductive layers.
Contact:Opening in an insulating film to allow contact to an underlying electronic device.
The placement of vias directly over the contacts or other,lower vias is known as stacked via.

14) Why is it that NMOS transistors can be created directly in a P-type
substrate, whereas PMOS transistors must be created in an N-type well?

15) Why must transistors be provided with "bulk" connections? What voltage
levels are connected to a p-type substrate and an n-type well through these
connections, and why?

To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit

16) What are process design rules? What is their major purpose? How are
design rules created?

17) What are width rules, space rules, and overlap rules?

8) What is a "vertical connection diagram"? What is it used for?

vertical connection diagram illustrates the relative position, going
vertically, of all the drawn layers. Such diagrams are especially
useful in complex processses, such as DRAM processes.

19) The routing strategies for the power grid and global signals are usually
defined at the start of planning a new chip floorplan. Why?

20) What are the major advantages of hierarchical IC design?

Concurrent design
• Design reuse
• Predictable schedules

21) Define what is meant by the terms design rules checking, layout versus
schematic, and electrical rules check? Are all three procedures required
in every chip design?

22) What is meant by the term "porosity"? Why is it desirable for a cell
or macro to have high porosity?

23) What are the main differences in priorities between microprocessor design,
ASIC design, and memory design? How are those differences reflected in
the corresponding design flows?

24) What is an "application-specific memory", according to Clein? What are
some specific examples of this part type?

25) What is the difference between a soft IP block (soft core) and a hard
IP block (hard core)?

Softcore
- most flexible
- exist either as a gate-netlist or RTL.

Hardcare
- best for plug and play
- less portable and less flexible.
- physical manifestations of the IP design.


26) In ASIC design, what are the main advantages of expressing the design
using a hardware description language, such as VHDL or Verilog?

The main reason for using high level hardware design like VHDL or Verilog is
easy generating hundred of million gate counts chip better than schematic entry
design.

27) Why are memory layouts designed primarily from the bottom up, instead of
from the top down, like other ICs?

28) With respect to a memory layout, what is meant by "array efficiency"?

29) What is "pitch-limited layout"? What are some of the major circuits
in a memory layout that must meet pitch-limited constraints?

30) What are some of the typical kinds of cells that one would expect to
find in a library of standard cells?

31) The layout of standard cells is constrained to simplify the job of
place & route tools. Give several examples of these constraints.

32) Why did older cell libraries include so-called feedthrough cells? Why
are such cells no longer required in cell libraries for modern processes?

33) What is electromigration? How does electromigration affect the design of
a standard cell based design?

34) What is a gate array? Why are main advantages of using gate arrays to
implement an IC? What are some of the main disadvantages, with respect to
custom design or standard cell based design?

35) Why might one want to use some gate array based design inside an otherwise
custom IC design, according to Clein's experience?

36) What are some of the major similarities and differences of standard cells
and datapath cells?

37) How is the problem of driving a clock node different from that of

designing
a regular signal node? What are the key goals when laying out a clock node?

38)What is a "pad frame"? What are "staggered" pads?

39) Why are 90 degree corners usually avoided in the layout of pad cells?

40) In the layout of output pad driver transistors, why is the gate length
often lengthened at both ends of the gate?

41) Why is the pad ring provided with power supply connections that are
separate from those of the core design?

42) What are so-called friendly cells in a DRAM core design? Why and where these cells included in a memory design?

43) Why are metal straps used along with polysilicon wordlines in memory designs?

44) Why are wordline driver circuits very long and narrow?

45) Describe some of the alignment keys that are included in IC layouts.

46) Why is the power supply interconnect layout layout planned out before other elements? Similarly, why are busses, differential signals, and shielded signals routed before other general signals?

47) What are the root and resistance styles of power supply layout?

4Cool What are some of the main reasons why clock skew minimization is such a major design challenge?

49) What are the major advantages and disadvantages of using a single clock tree conductor driven by one big buffer?

50) In ASIC design flows, why are clock trees inserted after the logic cells have been placed? In such clock trees, how is clock skew minimized at the leaves of the tree?

61) Explain what is meant by electromigration. What are some possible
consequences of unexpectedly high electromigration? How is electromigration
controlled in IC layout design?

62) Why are wide metal conductors, such as those in the power rings, provided
with slits? What constraints must be followed when positioning these slits?

63) When placing multiple vias to connect two metal conductors, why is it better to space the vias far apart from each other?

64) Why would a DRAM layout be verified against two or more different sets of design rules?

65) What is the antenna effect, and how can it cause problems in an IC design? What are two layout techniques that can be used to reduce vulnerability to the antenna effect?

66) What is the purpose of minimum area design rules?

67) What is the purpose of end overlap rules?

68) What is the phenomenon of latch-up? Why is it a serious concern in CMOS layout design?

69) Describe six different layout strategies that are commonly used to minimize
the possibility of latch-up.

70) Why is it wise to plan designs to make it easier to change details later?

71) What is meant by metal strap programmability and via programmability?
Give one example where each techniques is commonly used.

72) What is the difference between test pads and probe pads?

73) Dan Clein advocates the use of contact and via cells, which is not a common design practice. What are his reasons?

74) In which situation should one avoid using the minimum allowed feature sizes
allowed by the design rules?

75) What fundamental factors limits the speed with which detected design errors can be corrected?

76) When floorplanning a chip at the start of the IC layout process, what are the main goals in deciding how to arrange the major blocks in the design? power line, noise, clock tree?!

77) How is block floorplanning different from chip floorplanning?

78)What is a silicon compiler? How is it different from a tiler?

79) What is the difference between a channel router and a maze router?
Which type of router will tend to produce higher utilization factors?

80) What is a chip assembly tool? What kind of routing should a chip

assembly
tool provide to have maximum flexibility?

81) At IBM, it has been found to be advantageous to sacrifice performance

when
migrating a chip design in one process into a second process. Process

migration
is facilitated by the use of "migratable design rules". What is the major
benefit that can be obtained by such rules to offset the loss in potential
chip performance?

82) At IBM a design methodology has been developed that makes the layout of standard cells very similar to that of gate array cells. What is the potential benefit of intermixing such cells in the same chip design?

83) In its ASIC design flow, IBM uses a formal verification tool that performs
a technique called Boolean equivalence checking. What is the primary potential
benefit of using formal verification methods in design verification? What is the conventional way of verifying the equivalence of different implementations of the same function?

84) IBM has standardized its logic design on the use of pulse-triggered latches,
whereas the rest of the industry has tended to adopted design based on edge- triggered flip-flops. What is the strategy that IBM has adopted to be able to accommodate designers from other companies who wish to have ASICs fabricated
through IBM?

85) Why are terminator cells sometimes used when clock trees are inserted into
a block of placed standard cells?

86) When constructing a clock tree with distributed buffers, why is it very
desirable to keep the buffers lightly loaded near the root of the clock
distribution tree? Why can leaf nodes of the clock tree can be loaded more
heavily? Why does one aim to have a balanced clock tree?

88) Guard bands are usually built into the timing estimates employed by logic
synthesis, cell placers, and other CAD tools. What is lost when the guard bands are relatively large? What could be gained if the timing estimates could be made more accurate?

89) Full 3-D capacitance calculations are generally extremely timing consuming.
How can the technique of tunneling be used to make such calculations efficient
enough to use in large IC designs?

89) The output of a 3-D field solver is a charge distribution over the signal
net under consideration, and a charge distribution over the surrounding passive
nets. Generally the signal net is assumed to be at a potential of 1 volt while
the other nets are held at 0 volts. How can the signal net's self-capacitance
and coupling capacitance then be computed?

90) Moore's Law predicts a doubling in the number of transistors per chip every
two to three years. The major factor supporting Moore's Law is improvements in lithographic resolution that permit finer features. What are the two other major factors that Moore believes have allowed Moore's Law to hold? Even if physical factors allow for further increases in per-chip component density, what other factors could slow or even stop Moore's Law in practice?

91) What is meant by the term "dual damascene process"? How has the availability of this type of process simplified the creation of multiple interconnected metal layers?

92) In processes that have multiple layers of metal interconnect, why is it
common to make the upper wires thicker than the lower layers? (The use of
fat wires is sometimes called "reverse scaling".) In which situations would
one be willing to use reverse scaling and hence appear to throw away the
possible advantages of thinner wires?

93) What are some of the important reasons why DRAM technology has been
a pioneer for semiconductor technology advances?

94) Briefly explain what are planar DRAM cells, trench capacitor DRAM