1. Explain why & how a MOSFET works
2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
3. Explain the various MOSFET Capacitances & their significance
4. Draw a CMOS Inverter. Explain its transfer characteristics
5. Explain sizing of the inverter
6. How do you size NMOS and PMOS transistors to increase the threshold voltage?
7. What is Noise Margin? Explain the procedure to determine Noise Margin
8. Give the expression for CMOS switching power dissipation
9. What is Body Effect?
10. Describe the various effects of scaling
11. Give the expression for calculating Delay in CMOS circuit
12. What happens to delay if you increase load capacitance?
13. What happens to delay if we include a resistance at the output of a CMOS circuit?
14. What are the limitations in increasing the power supply to reduce delay?
15. How does Resistance of the metal lines vary with increasing thickness and increasing length?
16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
17. What happens if we increase the number of contacts or via from one metal layer to the next?
18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
20. Draw the stick diagram of a NOR gate. Optimize it
21. For CMOS logic, give the various techniques you know to minimize power consumption
22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
27. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write operations
30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential Sense Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?
35. What’s the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
39. How can you model a SRAM at RTL Level?
40. What’s the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Thursday, August 21, 2008
Wednesday, August 13, 2008
Layout Interview Questions BY Poornima Jenaras -Bangalore-VLSI Designers
**THIS SERIES DONATED BY Poornima Jenaras in our ORKUT GROUP Bangalore-VLSI Designers **
1) According to Clein, what has been one of the main reasons why CAD tools have failed to be successful among IC layout engineers?
2) With respect to CAD tools, what are some of the advantanges and disadvantages to being a small IC design house?
advantages:good integration of tools and service cut off their time wasted on tools
disadvantages:too expensive
3) What is an IC design flow? Why do IC design teams operate within the constraints of design flows?
Constrain in a flow in order to integrating different part of a system and with expected results
4) Why are PMOS transistor networks generally used to produce high (i.e. 1) signals, while NMOS networks are used to product low (0) signals?
PMOS is used to drive 'high' because of the thresholdvoltage-effect The same is true for NMOS to drive 'low'.
A NMOS device cant drive a full '1' and PMOS cant drive full '0'Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing
5) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean?
The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)
If given only one number it's the width combined with a default length
6) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates) usually limited to four?
To limit the height of the stack.
As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be.
7) What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero?
8) What is a transmission gate, and what is it used for typically? Why
are transmission gates made with both PMOS and NMOS transistors?
9) What are the major factors that determine the speed that a logic signal
propagates from the input of one gate to the input of the next driven gate
in the signal's path?
10) What are some of the major techniques that are usually considered when
one wants to speed up the propagation speed of a signal?
11) What is the difference between a mask layer and a drawn layer in an
IC layout? Why do layout designers usually only specify drawn layers?
12) In an IC layout, what is a polygon and what is a path? What are the
advantages and disadvantages of each?
A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it's off grid with 45 degree angle. Polygon is always on-grid, unless it's a copy and flip. However, polygon is hard to edit and work with.
13) What is the difference between a contact and a via? What is a "stacked" via process?
Via: a contact between two conductive layers.
Contact:Opening in an insulating film to allow contact to an underlying electronic device.
The placement of vias directly over the contacts or other,lower vias is known as stacked via.
14) Why is it that NMOS transistors can be created directly in a P-type
substrate, whereas PMOS transistors must be created in an N-type well?
15) Why must transistors be provided with "bulk" connections? What voltage
levels are connected to a p-type substrate and an n-type well through these
connections, and why?
To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit
16) What are process design rules? What is their major purpose? How are
design rules created?
17) What are width rules, space rules, and overlap rules?
8) What is a "vertical connection diagram"? What is it used for?
vertical connection diagram illustrates the relative position, going
vertically, of all the drawn layers. Such diagrams are especially
useful in complex processses, such as DRAM processes.
19) The routing strategies for the power grid and global signals are usually
defined at the start of planning a new chip floorplan. Why?
20) What are the major advantages of hierarchical IC design?
Concurrent design
• Design reuse
• Predictable schedules
21) Define what is meant by the terms design rules checking, layout versus
schematic, and electrical rules check? Are all three procedures required
in every chip design?
22) What is meant by the term "porosity"? Why is it desirable for a cell
or macro to have high porosity?
23) What are the main differences in priorities between microprocessor design,
ASIC design, and memory design? How are those differences reflected in
the corresponding design flows?
24) What is an "application-specific memory", according to Clein? What are
some specific examples of this part type?
25) What is the difference between a soft IP block (soft core) and a hard
IP block (hard core)?
Softcore
- most flexible
- exist either as a gate-netlist or RTL.
Hardcare
- best for plug and play
- less portable and less flexible.
- physical manifestations of the IP design.
26) In ASIC design, what are the main advantages of expressing the design
using a hardware description language, such as VHDL or Verilog?
The main reason for using high level hardware design like VHDL or Verilog is
easy generating hundred of million gate counts chip better than schematic entry
design.
27) Why are memory layouts designed primarily from the bottom up, instead of
from the top down, like other ICs?
28) With respect to a memory layout, what is meant by "array efficiency"?
29) What is "pitch-limited layout"? What are some of the major circuits
in a memory layout that must meet pitch-limited constraints?
30) What are some of the typical kinds of cells that one would expect to
find in a library of standard cells?
31) The layout of standard cells is constrained to simplify the job of
place & route tools. Give several examples of these constraints.
32) Why did older cell libraries include so-called feedthrough cells? Why
are such cells no longer required in cell libraries for modern processes?
33) What is electromigration? How does electromigration affect the design of
a standard cell based design?
34) What is a gate array? Why are main advantages of using gate arrays to
implement an IC? What are some of the main disadvantages, with respect to
custom design or standard cell based design?
35) Why might one want to use some gate array based design inside an otherwise
custom IC design, according to Clein's experience?
36) What are some of the major similarities and differences of standard cells
and datapath cells?
37) How is the problem of driving a clock node different from that of
designing
a regular signal node? What are the key goals when laying out a clock node?
38)What is a "pad frame"? What are "staggered" pads?
39) Why are 90 degree corners usually avoided in the layout of pad cells?
40) In the layout of output pad driver transistors, why is the gate length
often lengthened at both ends of the gate?
41) Why is the pad ring provided with power supply connections that are
separate from those of the core design?
42) What are so-called friendly cells in a DRAM core design? Why and where these cells included in a memory design?
43) Why are metal straps used along with polysilicon wordlines in memory designs?
44) Why are wordline driver circuits very long and narrow?
45) Describe some of the alignment keys that are included in IC layouts.
46) Why is the power supply interconnect layout layout planned out before other elements? Similarly, why are busses, differential signals, and shielded signals routed before other general signals?
47) What are the root and resistance styles of power supply layout?
4Cool What are some of the main reasons why clock skew minimization is such a major design challenge?
49) What are the major advantages and disadvantages of using a single clock tree conductor driven by one big buffer?
50) In ASIC design flows, why are clock trees inserted after the logic cells have been placed? In such clock trees, how is clock skew minimized at the leaves of the tree?
61) Explain what is meant by electromigration. What are some possible
consequences of unexpectedly high electromigration? How is electromigration
controlled in IC layout design?
62) Why are wide metal conductors, such as those in the power rings, provided
with slits? What constraints must be followed when positioning these slits?
63) When placing multiple vias to connect two metal conductors, why is it better to space the vias far apart from each other?
64) Why would a DRAM layout be verified against two or more different sets of design rules?
65) What is the antenna effect, and how can it cause problems in an IC design? What are two layout techniques that can be used to reduce vulnerability to the antenna effect?
66) What is the purpose of minimum area design rules?
67) What is the purpose of end overlap rules?
68) What is the phenomenon of latch-up? Why is it a serious concern in CMOS layout design?
69) Describe six different layout strategies that are commonly used to minimize
the possibility of latch-up.
70) Why is it wise to plan designs to make it easier to change details later?
71) What is meant by metal strap programmability and via programmability?
Give one example where each techniques is commonly used.
72) What is the difference between test pads and probe pads?
73) Dan Clein advocates the use of contact and via cells, which is not a common design practice. What are his reasons?
74) In which situation should one avoid using the minimum allowed feature sizes
allowed by the design rules?
75) What fundamental factors limits the speed with which detected design errors can be corrected?
76) When floorplanning a chip at the start of the IC layout process, what are the main goals in deciding how to arrange the major blocks in the design? power line, noise, clock tree?!
77) How is block floorplanning different from chip floorplanning?
78)What is a silicon compiler? How is it different from a tiler?
79) What is the difference between a channel router and a maze router?
Which type of router will tend to produce higher utilization factors?
80) What is a chip assembly tool? What kind of routing should a chip
assembly
tool provide to have maximum flexibility?
81) At IBM, it has been found to be advantageous to sacrifice performance
when
migrating a chip design in one process into a second process. Process
migration
is facilitated by the use of "migratable design rules". What is the major
benefit that can be obtained by such rules to offset the loss in potential
chip performance?
82) At IBM a design methodology has been developed that makes the layout of standard cells very similar to that of gate array cells. What is the potential benefit of intermixing such cells in the same chip design?
83) In its ASIC design flow, IBM uses a formal verification tool that performs
a technique called Boolean equivalence checking. What is the primary potential
benefit of using formal verification methods in design verification? What is the conventional way of verifying the equivalence of different implementations of the same function?
84) IBM has standardized its logic design on the use of pulse-triggered latches,
whereas the rest of the industry has tended to adopted design based on edge- triggered flip-flops. What is the strategy that IBM has adopted to be able to accommodate designers from other companies who wish to have ASICs fabricated
through IBM?
85) Why are terminator cells sometimes used when clock trees are inserted into
a block of placed standard cells?
86) When constructing a clock tree with distributed buffers, why is it very
desirable to keep the buffers lightly loaded near the root of the clock
distribution tree? Why can leaf nodes of the clock tree can be loaded more
heavily? Why does one aim to have a balanced clock tree?
88) Guard bands are usually built into the timing estimates employed by logic
synthesis, cell placers, and other CAD tools. What is lost when the guard bands are relatively large? What could be gained if the timing estimates could be made more accurate?
89) Full 3-D capacitance calculations are generally extremely timing consuming.
How can the technique of tunneling be used to make such calculations efficient
enough to use in large IC designs?
89) The output of a 3-D field solver is a charge distribution over the signal
net under consideration, and a charge distribution over the surrounding passive
nets. Generally the signal net is assumed to be at a potential of 1 volt while
the other nets are held at 0 volts. How can the signal net's self-capacitance
and coupling capacitance then be computed?
90) Moore's Law predicts a doubling in the number of transistors per chip every
two to three years. The major factor supporting Moore's Law is improvements in lithographic resolution that permit finer features. What are the two other major factors that Moore believes have allowed Moore's Law to hold? Even if physical factors allow for further increases in per-chip component density, what other factors could slow or even stop Moore's Law in practice?
91) What is meant by the term "dual damascene process"? How has the availability of this type of process simplified the creation of multiple interconnected metal layers?
92) In processes that have multiple layers of metal interconnect, why is it
common to make the upper wires thicker than the lower layers? (The use of
fat wires is sometimes called "reverse scaling".) In which situations would
one be willing to use reverse scaling and hence appear to throw away the
possible advantages of thinner wires?
93) What are some of the important reasons why DRAM technology has been
a pioneer for semiconductor technology advances?
94) Briefly explain what are planar DRAM cells, trench capacitor DRAM
1) According to Clein, what has been one of the main reasons why CAD tools have failed to be successful among IC layout engineers?
2) With respect to CAD tools, what are some of the advantanges and disadvantages to being a small IC design house?
advantages:good integration of tools and service cut off their time wasted on tools
disadvantages:too expensive
3) What is an IC design flow? Why do IC design teams operate within the constraints of design flows?
Constrain in a flow in order to integrating different part of a system and with expected results
4) Why are PMOS transistor networks generally used to produce high (i.e. 1) signals, while NMOS networks are used to product low (0) signals?
PMOS is used to drive 'high' because of the thresholdvoltage-effect The same is true for NMOS to drive 'low'.
A NMOS device cant drive a full '1' and PMOS cant drive full '0'Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing
5) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean?
The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)
If given only one number it's the width combined with a default length
6) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates) usually limited to four?
To limit the height of the stack.
As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be.
7) What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero?
8) What is a transmission gate, and what is it used for typically? Why
are transmission gates made with both PMOS and NMOS transistors?
9) What are the major factors that determine the speed that a logic signal
propagates from the input of one gate to the input of the next driven gate
in the signal's path?
10) What are some of the major techniques that are usually considered when
one wants to speed up the propagation speed of a signal?
11) What is the difference between a mask layer and a drawn layer in an
IC layout? Why do layout designers usually only specify drawn layers?
12) In an IC layout, what is a polygon and what is a path? What are the
advantages and disadvantages of each?
A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it's off grid with 45 degree angle. Polygon is always on-grid, unless it's a copy and flip. However, polygon is hard to edit and work with.
13) What is the difference between a contact and a via? What is a "stacked" via process?
Via: a contact between two conductive layers.
Contact:Opening in an insulating film to allow contact to an underlying electronic device.
The placement of vias directly over the contacts or other,lower vias is known as stacked via.
14) Why is it that NMOS transistors can be created directly in a P-type
substrate, whereas PMOS transistors must be created in an N-type well?
15) Why must transistors be provided with "bulk" connections? What voltage
levels are connected to a p-type substrate and an n-type well through these
connections, and why?
To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit
16) What are process design rules? What is their major purpose? How are
design rules created?
17) What are width rules, space rules, and overlap rules?
8) What is a "vertical connection diagram"? What is it used for?
vertical connection diagram illustrates the relative position, going
vertically, of all the drawn layers. Such diagrams are especially
useful in complex processses, such as DRAM processes.
19) The routing strategies for the power grid and global signals are usually
defined at the start of planning a new chip floorplan. Why?
20) What are the major advantages of hierarchical IC design?
Concurrent design
• Design reuse
• Predictable schedules
21) Define what is meant by the terms design rules checking, layout versus
schematic, and electrical rules check? Are all three procedures required
in every chip design?
22) What is meant by the term "porosity"? Why is it desirable for a cell
or macro to have high porosity?
23) What are the main differences in priorities between microprocessor design,
ASIC design, and memory design? How are those differences reflected in
the corresponding design flows?
24) What is an "application-specific memory", according to Clein? What are
some specific examples of this part type?
25) What is the difference between a soft IP block (soft core) and a hard
IP block (hard core)?
Softcore
- most flexible
- exist either as a gate-netlist or RTL.
Hardcare
- best for plug and play
- less portable and less flexible.
- physical manifestations of the IP design.
26) In ASIC design, what are the main advantages of expressing the design
using a hardware description language, such as VHDL or Verilog?
The main reason for using high level hardware design like VHDL or Verilog is
easy generating hundred of million gate counts chip better than schematic entry
design.
27) Why are memory layouts designed primarily from the bottom up, instead of
from the top down, like other ICs?
28) With respect to a memory layout, what is meant by "array efficiency"?
29) What is "pitch-limited layout"? What are some of the major circuits
in a memory layout that must meet pitch-limited constraints?
30) What are some of the typical kinds of cells that one would expect to
find in a library of standard cells?
31) The layout of standard cells is constrained to simplify the job of
place & route tools. Give several examples of these constraints.
32) Why did older cell libraries include so-called feedthrough cells? Why
are such cells no longer required in cell libraries for modern processes?
33) What is electromigration? How does electromigration affect the design of
a standard cell based design?
34) What is a gate array? Why are main advantages of using gate arrays to
implement an IC? What are some of the main disadvantages, with respect to
custom design or standard cell based design?
35) Why might one want to use some gate array based design inside an otherwise
custom IC design, according to Clein's experience?
36) What are some of the major similarities and differences of standard cells
and datapath cells?
37) How is the problem of driving a clock node different from that of
designing
a regular signal node? What are the key goals when laying out a clock node?
38)What is a "pad frame"? What are "staggered" pads?
39) Why are 90 degree corners usually avoided in the layout of pad cells?
40) In the layout of output pad driver transistors, why is the gate length
often lengthened at both ends of the gate?
41) Why is the pad ring provided with power supply connections that are
separate from those of the core design?
42) What are so-called friendly cells in a DRAM core design? Why and where these cells included in a memory design?
43) Why are metal straps used along with polysilicon wordlines in memory designs?
44) Why are wordline driver circuits very long and narrow?
45) Describe some of the alignment keys that are included in IC layouts.
46) Why is the power supply interconnect layout layout planned out before other elements? Similarly, why are busses, differential signals, and shielded signals routed before other general signals?
47) What are the root and resistance styles of power supply layout?
4Cool What are some of the main reasons why clock skew minimization is such a major design challenge?
49) What are the major advantages and disadvantages of using a single clock tree conductor driven by one big buffer?
50) In ASIC design flows, why are clock trees inserted after the logic cells have been placed? In such clock trees, how is clock skew minimized at the leaves of the tree?
61) Explain what is meant by electromigration. What are some possible
consequences of unexpectedly high electromigration? How is electromigration
controlled in IC layout design?
62) Why are wide metal conductors, such as those in the power rings, provided
with slits? What constraints must be followed when positioning these slits?
63) When placing multiple vias to connect two metal conductors, why is it better to space the vias far apart from each other?
64) Why would a DRAM layout be verified against two or more different sets of design rules?
65) What is the antenna effect, and how can it cause problems in an IC design? What are two layout techniques that can be used to reduce vulnerability to the antenna effect?
66) What is the purpose of minimum area design rules?
67) What is the purpose of end overlap rules?
68) What is the phenomenon of latch-up? Why is it a serious concern in CMOS layout design?
69) Describe six different layout strategies that are commonly used to minimize
the possibility of latch-up.
70) Why is it wise to plan designs to make it easier to change details later?
71) What is meant by metal strap programmability and via programmability?
Give one example where each techniques is commonly used.
72) What is the difference between test pads and probe pads?
73) Dan Clein advocates the use of contact and via cells, which is not a common design practice. What are his reasons?
74) In which situation should one avoid using the minimum allowed feature sizes
allowed by the design rules?
75) What fundamental factors limits the speed with which detected design errors can be corrected?
76) When floorplanning a chip at the start of the IC layout process, what are the main goals in deciding how to arrange the major blocks in the design? power line, noise, clock tree?!
77) How is block floorplanning different from chip floorplanning?
78)What is a silicon compiler? How is it different from a tiler?
79) What is the difference between a channel router and a maze router?
Which type of router will tend to produce higher utilization factors?
80) What is a chip assembly tool? What kind of routing should a chip
assembly
tool provide to have maximum flexibility?
81) At IBM, it has been found to be advantageous to sacrifice performance
when
migrating a chip design in one process into a second process. Process
migration
is facilitated by the use of "migratable design rules". What is the major
benefit that can be obtained by such rules to offset the loss in potential
chip performance?
82) At IBM a design methodology has been developed that makes the layout of standard cells very similar to that of gate array cells. What is the potential benefit of intermixing such cells in the same chip design?
83) In its ASIC design flow, IBM uses a formal verification tool that performs
a technique called Boolean equivalence checking. What is the primary potential
benefit of using formal verification methods in design verification? What is the conventional way of verifying the equivalence of different implementations of the same function?
84) IBM has standardized its logic design on the use of pulse-triggered latches,
whereas the rest of the industry has tended to adopted design based on edge- triggered flip-flops. What is the strategy that IBM has adopted to be able to accommodate designers from other companies who wish to have ASICs fabricated
through IBM?
85) Why are terminator cells sometimes used when clock trees are inserted into
a block of placed standard cells?
86) When constructing a clock tree with distributed buffers, why is it very
desirable to keep the buffers lightly loaded near the root of the clock
distribution tree? Why can leaf nodes of the clock tree can be loaded more
heavily? Why does one aim to have a balanced clock tree?
88) Guard bands are usually built into the timing estimates employed by logic
synthesis, cell placers, and other CAD tools. What is lost when the guard bands are relatively large? What could be gained if the timing estimates could be made more accurate?
89) Full 3-D capacitance calculations are generally extremely timing consuming.
How can the technique of tunneling be used to make such calculations efficient
enough to use in large IC designs?
89) The output of a 3-D field solver is a charge distribution over the signal
net under consideration, and a charge distribution over the surrounding passive
nets. Generally the signal net is assumed to be at a potential of 1 volt while
the other nets are held at 0 volts. How can the signal net's self-capacitance
and coupling capacitance then be computed?
90) Moore's Law predicts a doubling in the number of transistors per chip every
two to three years. The major factor supporting Moore's Law is improvements in lithographic resolution that permit finer features. What are the two other major factors that Moore believes have allowed Moore's Law to hold? Even if physical factors allow for further increases in per-chip component density, what other factors could slow or even stop Moore's Law in practice?
91) What is meant by the term "dual damascene process"? How has the availability of this type of process simplified the creation of multiple interconnected metal layers?
92) In processes that have multiple layers of metal interconnect, why is it
common to make the upper wires thicker than the lower layers? (The use of
fat wires is sometimes called "reverse scaling".) In which situations would
one be willing to use reverse scaling and hence appear to throw away the
possible advantages of thinner wires?
93) What are some of the important reasons why DRAM technology has been
a pioneer for semiconductor technology advances?
94) Briefly explain what are planar DRAM cells, trench capacitor DRAM
Tuesday, August 12, 2008
Semiconductor device fabrication
Semiconductor device fabrication is the process used to create chips, the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is the most commonly used semiconductor material today, along with various compound semiconductors.
The entire manufacturing process from start to packaged chips ready for shipment takes six to eight weeks and is performed in highly specialized facilities referred to as fabs.
Wafers
Main article: wafer (semiconductor)
A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.
Once the wafers are prepared, many process steps are necessary to produce the desired semiconductor integrated circuit. In general, the steps can be grouped into two areas:
* Front end processing
* Back end processing
Processing
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
* Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.
* Removal processes are any that remove material from the wafer either in bulk or selectively and consist primarily of etch processes, either wet etching or dry etching. Chemical-mechanical planarization (CMP) is also a removal process used between levels.
* Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a “photoresist”. The photoresist is exposed by a “stepper”, a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.
* Modification of electrical properties has historically consisted of doping transistor sources and drains originally by diffusion furnaces and later by ion implantation. These doping processes are followed by furnace anneal or in advanced devices, by rapid thermal anneal (RTA) which serve to activate the implanted dopants. Modification of electrical properties now also extends to reduction of dielectric constant in low-k insulating materials via exposure to ultraviolet light in UV processing (UVP).
Many modern chips have eight or more levels produced in over 300 sequenced processing steps.
Front End Processing
"Front End Processing" refers to the formation of the transistors directly on the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a "straining step" wherein a silicon variant such as "silicon-germanium" (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called "silicon on insulator" technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.
Silicon dioxide
Front end surface engineering is followed by: growth of the gate dielectric, traditionally silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In memory devices, storage cells, conventionally capacitors, are also fabricated at this time, either into the silicon surface or stacked above the transistor.
Metal layers
Once the various semiconductor devices have been created they must be interconnected to form the desired electrical circuits. This "Back End Of Line" (BEOL – the latter portion of the front end of wafer fabrication, not to be confused with "back end" of chip fabrication which refers to the package and test stages) involves creating metal interconnecting wires that are isolated by insulating dielectrics. The insulating material was traditionally a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used. These dielectrics presently take the form of SiOC and have dielectric constants around 2.7 (compared to 3.9 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.
Interconnect
Historically, the metal wires consisted of aluminium. In this approach to wiring often called "subtractive aluminium", blanket films of aluminium are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes, called "vias," in the insulating material and depositing tungsten in them with a CVD technique. This approach is still used in the fabrication of many memory chips such as dynamic random access memory (DRAM) as the number of interconnect levels is small, currently no more than four.
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become significant prompting a change in wiring material from aluminium to copper and from the silicon dioxides to newer high-K material. This performance enhancement also comes at a reduced cost via damascene processing that eliminates processing steps. In damascene processing, in contrast to subtractive aluminium technology, the dielectric material is deposited first as a blanket film and is patterned and etched leaving holes or trenches. In "single damascene" processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire "lines" respectively. In "dual damascene" technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both the via and line simultaneously, further reducing the number of processing steps. The thin barrier film, called Copper Barrier Seed (CBS), is necessary to prevent copper diffusion into the dielectric. The ideal barrier film is effective, but is barely there. As the presence of excessive barrier film competes with the available copper wire cross section, formation of the thinnest yet continuous barrier represents one of the greatest ongoing challenges in copper processing today.
As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked and extend outside the depth of focus of available lithography, interfering with the ability to pattern. CMP (Chemical Mechanical Polishing) is the primary processing method to achieve such planarization although dry "etch back" is still sometimes employed if the number of interconnect levels is no more than three.
Wafer test
The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. Wafer test metrology equipment is used to verify that the wafers are still good and haven't been damaged by previous processing steps. If the number of dies—the integrated circuits that will eventually become chips—on a wafer that measure as fails exceeds a predetermined threshold, the wafer is scrapped rather than investing in further processing.
Device test
Main article: wafer testing
Once the Front End Process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield.
The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. The fab charges for test time; the prices are on the order of cents per second. Chips are often designed with “testability features” such as "built-in self-test" to speed testing, and reduce test costs.
Good designs try to test and statistically manage corners: extremes of silicon behavior caused by operating temperature combined with the extremes of fab processing steps. Most designs cope with more than 64 corners.
Packaging
Main article: integrated circuit packaging
Once tested, the wafer is scored and then broken into individual die. Only the good, unmarked chips go on to be packaged.
Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny wires are used to connect pads to the pins. In the old days, wires were attached by hand, but now purpose-built machines perform the task. Traditionally, the wires to the chips were gold, leading to a “lead frame” (pronounced “leed frame”) of copper, that had been plated with solder, a mixture of tin and lead. Lead is poisonous, so lead-free “lead frames” are now mandated by ROHS.
Chip-scale package (CSP) is another packaging technology. Plastic packaged chips are usually considerably larger than the actual die, whereas CSP chips are nearly the size of the die. CSP can be constructed for each die before the wafer is diced [1].
The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser etches the chip’s name and numbers on the package.
List of steps
This is a list of processing techniques that are employed numerous times in a modern electronic device and do not necessarily imply a specific order.
* Wafer processing
o Wet cleans
o Photolithography
o Ion implantation (in which dopants are embedded in the wafer creating regions of increased (or decreased) conductivity)
o Dry etching
o Wet etching
o Plasma ashing
o Thermal treatments
+ Rapid thermal anneal
+ Furnace anneals
+ Thermal oxidation
o Chemical vapor deposition (CVD)
o Physical vapor deposition (PVD)
o Molecular beam epitaxy (MBE)
o Electrochemical Deposition (ECD). See Electroplating
o Chemical-mechanical planarization (CMP)
o Wafer testing (where the electrical performance is verified)
o Wafer backgrinding (to reduce the thickness of the wafer so the resulting chip can be put into a thin device like a smartcard or PCMCIA card.)
* Die preparation
o Wafer mounting
o Die cutting
* IC packaging
o Die attachment
o IC Bonding
+ Wire bonding
+ Flip chip
+ Tab bonding
o IC encapsulation
+ Baking
+ Plating
+ Lasermarking
+ Trim and form
* IC testing
Hazardous materials note
Many toxic materials are used in the fabrication process. These include:
* poisonous elemental dopants such as arsenic, boron, antimony and phosphorus
* poisonous compounds like arsine, phosphine and silane
* highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid and hydrofluoric acid
It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure of this sort. Most fabrication facillities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges etc, to control the risk to workers and also the environment if these toxic materials are released into the atmosphere. Some of these toxic materials, if released into the atmosphere, can remain there for thousands of years and contribute to global warming.
History
When feature widths were far greater than about 10 micrometres, purity was not the issue that it is today in device manufacturing. As devices became more integrated, cleanrooms became even cleaner. Today, the fabs are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination.
In an effort to increase profits, semiconductor device manufacturing has spread from Texas and California in the 1960s to the rest of the world, such as Ireland, Israel, Japan, Taiwan, Korea, Singapore and China. It is a global business today.
The leading semiconductor manufacturers typically have facilities all over the world. Intel, the world's largest manufacturer, has facilities in Europe and Asia as well as the U.S. Other top manufacturers include STMicroelectronics (Europe), Analog Devices (US/Asia), Atmel (US/Europe), Freescale Semiconductor (US), Samsung (Korea), Texas Instruments (US), Advanced Micro Devices (AMD) (US) see [2], Toshiba (Japan), NEC Electronics (Japan), Infineon (Europe), Renesas (Japan), Taiwan Semiconductor Manufacturing Company (Taiwan, see TSMC web site), Sony(Japan), NXP Semiconductors (Europe), Hynix (Korea) and SMIC (China, see SMIC web site).
The entire manufacturing process from start to packaged chips ready for shipment takes six to eight weeks and is performed in highly specialized facilities referred to as fabs.
Wafers
Main article: wafer (semiconductor)
A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.
Once the wafers are prepared, many process steps are necessary to produce the desired semiconductor integrated circuit. In general, the steps can be grouped into two areas:
* Front end processing
* Back end processing
Processing
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
* Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.
* Removal processes are any that remove material from the wafer either in bulk or selectively and consist primarily of etch processes, either wet etching or dry etching. Chemical-mechanical planarization (CMP) is also a removal process used between levels.
* Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a “photoresist”. The photoresist is exposed by a “stepper”, a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.
* Modification of electrical properties has historically consisted of doping transistor sources and drains originally by diffusion furnaces and later by ion implantation. These doping processes are followed by furnace anneal or in advanced devices, by rapid thermal anneal (RTA) which serve to activate the implanted dopants. Modification of electrical properties now also extends to reduction of dielectric constant in low-k insulating materials via exposure to ultraviolet light in UV processing (UVP).
Many modern chips have eight or more levels produced in over 300 sequenced processing steps.
Front End Processing
"Front End Processing" refers to the formation of the transistors directly on the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a "straining step" wherein a silicon variant such as "silicon-germanium" (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called "silicon on insulator" technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.
Silicon dioxide
Front end surface engineering is followed by: growth of the gate dielectric, traditionally silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In memory devices, storage cells, conventionally capacitors, are also fabricated at this time, either into the silicon surface or stacked above the transistor.
Metal layers
Once the various semiconductor devices have been created they must be interconnected to form the desired electrical circuits. This "Back End Of Line" (BEOL – the latter portion of the front end of wafer fabrication, not to be confused with "back end" of chip fabrication which refers to the package and test stages) involves creating metal interconnecting wires that are isolated by insulating dielectrics. The insulating material was traditionally a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used. These dielectrics presently take the form of SiOC and have dielectric constants around 2.7 (compared to 3.9 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.
Interconnect
Historically, the metal wires consisted of aluminium. In this approach to wiring often called "subtractive aluminium", blanket films of aluminium are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes, called "vias," in the insulating material and depositing tungsten in them with a CVD technique. This approach is still used in the fabrication of many memory chips such as dynamic random access memory (DRAM) as the number of interconnect levels is small, currently no more than four.
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become significant prompting a change in wiring material from aluminium to copper and from the silicon dioxides to newer high-K material. This performance enhancement also comes at a reduced cost via damascene processing that eliminates processing steps. In damascene processing, in contrast to subtractive aluminium technology, the dielectric material is deposited first as a blanket film and is patterned and etched leaving holes or trenches. In "single damascene" processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire "lines" respectively. In "dual damascene" technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both the via and line simultaneously, further reducing the number of processing steps. The thin barrier film, called Copper Barrier Seed (CBS), is necessary to prevent copper diffusion into the dielectric. The ideal barrier film is effective, but is barely there. As the presence of excessive barrier film competes with the available copper wire cross section, formation of the thinnest yet continuous barrier represents one of the greatest ongoing challenges in copper processing today.
As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked and extend outside the depth of focus of available lithography, interfering with the ability to pattern. CMP (Chemical Mechanical Polishing) is the primary processing method to achieve such planarization although dry "etch back" is still sometimes employed if the number of interconnect levels is no more than three.
Wafer test
The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. Wafer test metrology equipment is used to verify that the wafers are still good and haven't been damaged by previous processing steps. If the number of dies—the integrated circuits that will eventually become chips—on a wafer that measure as fails exceeds a predetermined threshold, the wafer is scrapped rather than investing in further processing.
Device test
Main article: wafer testing
Once the Front End Process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield.
The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. The fab charges for test time; the prices are on the order of cents per second. Chips are often designed with “testability features” such as "built-in self-test" to speed testing, and reduce test costs.
Good designs try to test and statistically manage corners: extremes of silicon behavior caused by operating temperature combined with the extremes of fab processing steps. Most designs cope with more than 64 corners.
Packaging
Main article: integrated circuit packaging
Once tested, the wafer is scored and then broken into individual die. Only the good, unmarked chips go on to be packaged.
Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny wires are used to connect pads to the pins. In the old days, wires were attached by hand, but now purpose-built machines perform the task. Traditionally, the wires to the chips were gold, leading to a “lead frame” (pronounced “leed frame”) of copper, that had been plated with solder, a mixture of tin and lead. Lead is poisonous, so lead-free “lead frames” are now mandated by ROHS.
Chip-scale package (CSP) is another packaging technology. Plastic packaged chips are usually considerably larger than the actual die, whereas CSP chips are nearly the size of the die. CSP can be constructed for each die before the wafer is diced [1].
The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser etches the chip’s name and numbers on the package.
List of steps
This is a list of processing techniques that are employed numerous times in a modern electronic device and do not necessarily imply a specific order.
* Wafer processing
o Wet cleans
o Photolithography
o Ion implantation (in which dopants are embedded in the wafer creating regions of increased (or decreased) conductivity)
o Dry etching
o Wet etching
o Plasma ashing
o Thermal treatments
+ Rapid thermal anneal
+ Furnace anneals
+ Thermal oxidation
o Chemical vapor deposition (CVD)
o Physical vapor deposition (PVD)
o Molecular beam epitaxy (MBE)
o Electrochemical Deposition (ECD). See Electroplating
o Chemical-mechanical planarization (CMP)
o Wafer testing (where the electrical performance is verified)
o Wafer backgrinding (to reduce the thickness of the wafer so the resulting chip can be put into a thin device like a smartcard or PCMCIA card.)
* Die preparation
o Wafer mounting
o Die cutting
* IC packaging
o Die attachment
o IC Bonding
+ Wire bonding
+ Flip chip
+ Tab bonding
o IC encapsulation
+ Baking
+ Plating
+ Lasermarking
+ Trim and form
* IC testing
Hazardous materials note
Many toxic materials are used in the fabrication process. These include:
* poisonous elemental dopants such as arsenic, boron, antimony and phosphorus
* poisonous compounds like arsine, phosphine and silane
* highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid and hydrofluoric acid
It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure of this sort. Most fabrication facillities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges etc, to control the risk to workers and also the environment if these toxic materials are released into the atmosphere. Some of these toxic materials, if released into the atmosphere, can remain there for thousands of years and contribute to global warming.
History
When feature widths were far greater than about 10 micrometres, purity was not the issue that it is today in device manufacturing. As devices became more integrated, cleanrooms became even cleaner. Today, the fabs are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination.
In an effort to increase profits, semiconductor device manufacturing has spread from Texas and California in the 1960s to the rest of the world, such as Ireland, Israel, Japan, Taiwan, Korea, Singapore and China. It is a global business today.
The leading semiconductor manufacturers typically have facilities all over the world. Intel, the world's largest manufacturer, has facilities in Europe and Asia as well as the U.S. Other top manufacturers include STMicroelectronics (Europe), Analog Devices (US/Asia), Atmel (US/Europe), Freescale Semiconductor (US), Samsung (Korea), Texas Instruments (US), Advanced Micro Devices (AMD) (US) see [2], Toshiba (Japan), NEC Electronics (Japan), Infineon (Europe), Renesas (Japan), Taiwan Semiconductor Manufacturing Company (Taiwan, see TSMC web site), Sony(Japan), NXP Semiconductors (Europe), Hynix (Korea) and SMIC (China, see SMIC web site).
Photolithography
Photolithography (also called optical lithography) is a process used in microfabrication to selectively remove parts of a thin film (or the bulk of a substrate). It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical (photoresist, or simply "resist") on the substrate. A series of chemical treatments then engraves the exposure pattern into the material underneath the photoresist. In a complex integrated circuit (for example, modern CMOS), a wafer will go through the photolithographic cycle up to 50 times.
Photolithography shares some fundamental principles with photography, in that the pattern in the etching resist is created by exposing it to light, either using a projected image or an optical mask. This step is like an ultra high precision version of the method used to make printed circuit boards. Subsequent stages in the process have more in common with etching than to lithographic printing. It is used because it affords exact control over the shape and size of the objects it creates, and because it can create patterns over an entire surface simultaneously. Its main disadvantages are that it requires a flat substrate to start with, it is not very effective at creating shapes that are not flat, and it can require extremely clean operating conditions.
Basic procedure
A single iteration of photolithography combines several steps in sequence. Modern cleanrooms use automated, robotic wafer track systems to coordinate the process. The procedure described here omits some advanced treatments, such as thinning agents or edge-bead removal. [1]
Preparation
The wafer is initially heated to a temperature sufficient to drive off any moisture that may be present on the wafer surface. Wafers that have been in storage must be chemically cleaned to remove contamination. A liquid or gaseous "adhesion promoter", such as hexamethyldisilazane (HMDS), is applied to promote adhesion of the photoresist to the wafer.
Photoresist application
The wafer is covered with photoresist ("PR") by spin coating. A viscous, liquid solution of photoresist is dispensed onto the wafer, and the wafer is spun rapidly to produce a uniformly thick layer. The spin coating typically runs at 1200 to 4800 rpm for 30 to 60 seconds, and produces a layer between 0.5 and 2.5 micrometres thick.
The photoresist-coated wafer is then "soft-baked" or "prebaked" to drive off excess solvent, typically at 90 to 100 °C for 5 to 30 minutes.[citation needed] Sometimes a nitrogen atmosphere is used.
Exposure and developing
After prebaking, the photoresist is exposed to a pattern of intense light. Optical lithography typically uses ultraviolet light (see below). Positive photoresist, the most common type, becomes chemically less stable when exposed; negative photoresist becomes more stable. This chemical change allows some of the photoresist to be removed by a special solution, called "developer" by analogy with photographic developer. A post-exposure bake is performed before developing, typically to help reduce standing wave phenomena caused by the destructive and constructive interference patterns of the incident light.
The develop chemistry is delivered on a spinner, much like photoresist. Developers originally often contained sodium hydroxide (NaOH). However, sodium is considered an extremely undesirable contaminant in MOSFET fabrication because it degrades the insulating properties of gate oxides. Metal-ion-free developers such as tetramethylammonium hydroxide (TMAH) are now used.
The resulting wafer is then "hard-baked", typically at 120 to 180 °C[citation needed] for 20 to 30 minutes. The hard bake solidifies the remaining photoresist, to make a more durable protecting layer in future ion implantation, wet chemical etching, or plasma etching.
Etching
In the etching step, a liquid ("wet") or plasma ("dry") chemical agent removes the uppermost layer of the substrate in the areas that are not protected by photoresist. In semiconductor fabrication, dry etching techniques are generally used, as they can be made anisotropic, in order to avoid significant undercutting of the photoresist pattern. This is essential when the width of the features to be defined is similar to or less than the thickness of the material being etched (ie when the aspect ratio approaches unity). Wet etch processes are generally isotropic in nature, which is often indispensable for microelectromechanical systems, where suspended structures must be "released" from the underlying layer.
The development of low-defectivity anisotropic dry-etch process has enabled the ever-smaller features defined photolithographically in the resist to be transferred to the substrate material.
Photoresist removal
After a photoresist is no longer needed, it must be removed from the substrate. This usually requires a liquid "resist stripper", which chemically alters the resist so that it no longer adheres to the substrate. Alternatively, photoresist may be removed by a plasma containing oxygen, which oxidizes it. This process is called ashing, and resembles dry etching.
Exposure ("printing") systems
Exposure systems typically produce an image on the wafer using a photomask. The light shines through the photomask, which blocks it in some areas and lets it pass in others. (Maskless lithography projects a precise beam directly onto the wafer without using a mask, but it is not widely used in commercial processes.) Exposure systems may be classified by the optics that transfer the image from the mask to the wafer.
Contact and proximity
A contact printer, the simplest exposure system, puts a photomask in direct contact with the wafer and exposes it to a uniform light. A proximity printer puts a small gap between the photomask and wafer. In both cases, the mask covers the entire wafer, and simultaneously patterns every die.
Contact printing is liable to damage both the mask and the wafer, and this was the primary reason it was abandoned for high volume production. Both contact and proximity lithography require the light intensity to be uniform across an entire wafer, and the mask to align precisely to features already on the wafer. As modern processes use increasingly large wafers, these conditions become increasingly difficult.
Research and prototyping processes often use contact lithography, because it uses inexpensive hardware and can achieve high optical resolution. The resolution is approximately the square root of the product of the wavelength and the gap distance. Hence, contact printing offers the best resolution, because its gap distance is approximately zero (neglecting the thickness of the photoresist itself). In addition, nanoimprint lithography may revive interest in this familiar technique, especially since the cost of ownership is expected to be low.
Projection
- See also: Stepper
Very-large-scale integration lithography uses projection systems. Unlike contact or proximity masks, which cover an entire wafer, projection masks (also called "reticles") show only one die. Projection exposure systems (steppers) project the mask onto the wafer many times to create the complete pattern.
Photomasks
The image for the mask originates from a computerized data file. This data file is converted to a series of polygons and written onto a square fused quartz substrate covered with a layer of chrome using a photolithographic process. A beam of electrons is used to expose the pattern defined in the data file and travels over the surface of the substrate in either a vector or raster scan manner. Where the photoresist on the mask is exposed, the chrome can be etched away, leaving a clear path for the light in the stepper/scanner systems to travel through.
Resolution in projection systems
The ability to project a clear image of a small feature onto the wafer is limited by the wavelength of the light that is used, and the ability of the reduction lens system to capture enough diffraction orders from the illuminated mask. Current state-of-the-art photolithography tools use deep ultraviolet (DUV) light with wavelengths of 248 and 193 nm, which allow minimum feature sizes down to 50 nm.
The minimum feature size that a projection system can print is given approximately by:
where
is the minimum feature size (also called the critical dimension, target design rule). It is also common to write 2 times the half-pitch.
(commonly called k1 factor) is a coefficient that encapsulates process-related factors, and typically equals 0.4 for production
is the wavelength of light used
is the numerical aperture of the lens as seen from the wafer
According to this equation, minimum feature sizes can be decreased by decreasing the wavelength, and increasing the numerical aperture, i.e. making lenses larger and bringing them closer to the wafer. However, this design method runs into a competing constraint. In modern systems, the depth of focus is also a concern:
Here, 
is another process-related coefficient. The depth of focus restricts the thickness of the photoresist and the depth of the topography on the wafer. Chemical mechanical polishing is often used to flatten topography before high-resolution lithographic steps.
Light sources
Historically, photolithography has used ultraviolet light from gas-discharge lamps using mercury, sometimes in combination with noble gases such as xenon. These lamps produce light across a broad spectrum with several strong peaks in the ultraviolet range. This spectrum is filtered to select a single spectral line, usually the "g-line" (436 nm) or "i-line" (365 nm).
More recently, lithography has moved to "deep ultraviolet", produced by excimer lasers. (In lithography, wavelengths below 300 nm are called "deep UV".) Krypton fluoride produces a 248-nm spectral line, and argon fluoride a 193-nm line.
Optical lithography can be extended to feature sizes below 50 nm using 193 nm and liquid immersion techniques. Also termed immersion lithography, this enables the use of optics with numerical apertures exceeding 1.0. The liquid used is typically ultra-pure, deionised water, which provides for a refractive index above that of the usual air gap between the lens and the wafer surface. This is continually circulated to eliminate thermally-induced distortions. Water will only allow NA's of up to ~1.4, but materials with higher refractive indices will allow the effective NA to be increased further.
Tools using 157 nm wavelength DUV in a manner similar to current exposure systems have been developed. These were once targeted to succeed 193 nm at the 65 nm feature size node but have now all but been eliminated by the introduction of immersion lithography. This was due to persistent technical problems with the 157 nm technology and economic considerations that provided strong incentives for the continued use of 193 nm technology. High-index immersion lithography is the newest extension of 193 nm lithography to be considered. In 2006, features less than 30 nm were demonstrated by IBM using this technique[2].
Experimental methods
- See also: Nanolithography
Photolithography has been defeating predictions of its demise for many years. For instance, it was predicted that features smaller than 1 micrometre could not be printed optically. Modern techniques already print features with dimensions a fraction of the wavelength of light used - an amazing optical feat. Current research is exploring new tricks in the ultraviolet regime, as well as alternatives to conventional UV, such as electron beam lithography, X-ray lithography, extreme ultraviolet lithography, ion projection lithography, and immersion lithography.
Photo etching summary
Photo etching is a form of photochemical milling. It is a process commonly used in the creation of small, intricate parts, such as model cars. This process can be used in almost any industry that creates product out of small, thin metal sheets. The process is completed using the following steps:
- A sheet of metal is cleaned and prepped for the process by applying a photoresist coating, which makes the metal sensitive to light.
- The metal sheet is exposed to a UV light source. This is based on an image in a controlling computer, which is to match the end result of the process.
- By treating the metal in a developing solution, an image appears on the sheet of metal.
- Processing the metal with an etchant produces the desired design, based on the image on the exposed metal. Common etchants are hydrochloric acid, ammonium persulfate, and ferric chloride.
This process generally creates very exact, high quality cuts with a relatively fast turn around. Compared to other machining options, it is an economical alternative for machining flat parts.
Photomask
A photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. They are commonly used in photolithography.
Overview
Lithographic photomasks are typically transparent fused silica blanks covered with a pattern defined with a chrome metal absorbing film. Photomasks are used at wavelengths of 365 nm, 248 nm, and 193 nm. Photomasks have also been developed for other forms of radiation such as 157 nm, 13.5 nm (EUV), X-ray and electrons and ions, but these require entirely new materials for the substrate and the pattern film.
A set of photomasks, each defining a pattern layer in integrated circuit fabrication, is fed into a photolithography stepper or scanner and individually selected for exposure. In double patterning techniques, a photomask would correspond to a subset of the layer pattern.
In photolithography for the mass production of integrated circuit devices, the more correct term is usually photoreticle or simply reticle. In the case of a photomask, there is a one-to-one correspondence between the mask pattern and the wafer pattern. This was the standard for the 1:1 mask aligners that were succeeded by steppers and scanners with reduction optics. As used in steppers and scanners, the reticle commonly contains only one layer of the chip. (However, some photolithography fabs utilize reticles with more than one layer patterned onto the same mask). The pattern is projected and shrunk by four or five times onto the wafer surface. To achieve complete wafer coverage, the wafer is repeatedly 'stepped' from position to position under the optical column until full exposure is achieved.
Features 150 nm or below in size generally require phase-shifting to enhance the image quality to acceptable values. This can be achieved in many ways, but the two most common methods are to use an attenuated phase-shifting background film on the mask to increase the contrast of small intensity peaks, or to etch the exposed quartz so that the edge between the etched and unetched areas can be used to image nearly zero intensity. In the second case, unwanted edges would need to be trimmed out with another exposure. The former method is attenuated phase-shifting, and is often considered a weak enhancement, requiring special illumination for the most enhancement, while the latter method is known as alternating-aperture phase-shifting, and is the most popular strong enhancement technique.
As leading-edge semiconductor features shrink, photomask features which are 4× larger must inevitably shrink as well. This could pose challenges as the absorber film will need to become thinner, and hence less opaque. [1] A recent study by IMEC has found that thinner absorbers degrade image contrast and hence contribute to line-edge roughness, using state-of-the-art photolithography tools. [2] One possibility is to eliminate absorbers altogether and use 'chromeless' masks, relying solely on phase-shifting for imaging.
The emergence of immersion lithography has a strong impact on photomask requirements. The commonly used attenuated phase-shifting mask is more sensitive to the higher incidence angles applied in "hyper-NA" lithography, due to the longer optical path through the patterned film. [3]
Overview
Lithographic photomasks are typically transparent fused silica blanks covered with a pattern defined with a chrome metal absorbing film. Photomasks are used at wavelengths of 365 nm, 248 nm, and 193 nm. Photomasks have also been developed for other forms of radiation such as 157 nm, 13.5 nm (EUV), X-ray and electrons and ions, but these require entirely new materials for the substrate and the pattern film.
A set of photomasks, each defining a pattern layer in integrated circuit fabrication, is fed into a photolithography stepper or scanner and individually selected for exposure. In double patterning techniques, a photomask would correspond to a subset of the layer pattern.
In photolithography for the mass production of integrated circuit devices, the more correct term is usually photoreticle or simply reticle. In the case of a photomask, there is a one-to-one correspondence between the mask pattern and the wafer pattern. This was the standard for the 1:1 mask aligners that were succeeded by steppers and scanners with reduction optics. As used in steppers and scanners, the reticle commonly contains only one layer of the chip. (However, some photolithography fabs utilize reticles with more than one layer patterned onto the same mask). The pattern is projected and shrunk by four or five times onto the wafer surface. To achieve complete wafer coverage, the wafer is repeatedly 'stepped' from position to position under the optical column until full exposure is achieved.
Features 150 nm or below in size generally require phase-shifting to enhance the image quality to acceptable values. This can be achieved in many ways, but the two most common methods are to use an attenuated phase-shifting background film on the mask to increase the contrast of small intensity peaks, or to etch the exposed quartz so that the edge between the etched and unetched areas can be used to image nearly zero intensity. In the second case, unwanted edges would need to be trimmed out with another exposure. The former method is attenuated phase-shifting, and is often considered a weak enhancement, requiring special illumination for the most enhancement, while the latter method is known as alternating-aperture phase-shifting, and is the most popular strong enhancement technique.
As leading-edge semiconductor features shrink, photomask features which are 4× larger must inevitably shrink as well. This could pose challenges as the absorber film will need to become thinner, and hence less opaque. [1] A recent study by IMEC has found that thinner absorbers degrade image contrast and hence contribute to line-edge roughness, using state-of-the-art photolithography tools. [2] One possibility is to eliminate absorbers altogether and use 'chromeless' masks, relying solely on phase-shifting for imaging.
The emergence of immersion lithography has a strong impact on photomask requirements. The commonly used attenuated phase-shifting mask is more sensitive to the higher incidence angles applied in "hyper-NA" lithography, due to the longer optical path through the patterned film. [3]
GDSII
GDS II stream format, common acronym GDSII, is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photomasks.
History of the GDS II format
Initially, GDS II was designed as a format used to control integrated circuit photomask plotting. Despite its limited set of features and low data density, it became the industry conventional format for transfer of IC layout data between design tools of different vendors, all of which operated with proprietary data formats.
It was originally developed by Calma for its layout design software, "Graphic Data System" ("GDS") and "GDS II". Now the format is owned by Cadence Design Systems.
GDS II files are usually the final output product of the IC design cycle and are given to IC foundries for IC fabrication. GDS II files were originally placed on magnetic tapes. This moment was fittingly called tape out though it is not the original root of the term.
Objects contained in a GDS II file are grouped by assigning numeric attributes to them including "layer number", "datatype" or "texttype". While these attributes were designed to correspond to the "layers of material" used in manufacturing an integrated circuit, their meaning rapidly became more abstract to reflect the way that the physical layout is designed.
As of October 2004, many EDA software vendors have begun to support a new format, OASIS, which may replace GDS II.
GDS II utilities
As the GDS II stream format is the de facto standard, it is supported by nearly all EDA software. Beside the commercial vendors there are a plenty of free GDSII utilities [1]. These free tools includes editors [2], viewers [3], utilities to convert the 2D layout data into common 3D formats [4] [5], utilities to convert the binary format to a human readable ASCII format [6] and program libraries [7].
Notes
1. List of free GDSII utilities http://www.layouteditor.net/links
2. LayoutEditor, a free GDSII editor http://www.layouteditor.net
3. "KLayout" is a free GDSII viewer http://www.klayout.de
4. gds2pov easily convert GDSII data into a nicely rendered 3D view. http://www.atchoo.org/gds2pov
5. With GdsViewer tool, any portion of GDSII artwork can be exported to 3D VTK file. The latter can be viewed and manipulated with VTK compatible viewers, e.g. ParaView http://www.gbresearch.com/gdsviewer
6. GDS Utilities can convert binary GDSII files to ASCII representation, http://www.gbresearch.com/gdsutilities
7. Ruby GDSII Library for reading, manipulating, and writing GDSII data in the Ruby programming language http://www.rubyforge.org/projects/gdsii
History of the GDS II format
Initially, GDS II was designed as a format used to control integrated circuit photomask plotting. Despite its limited set of features and low data density, it became the industry conventional format for transfer of IC layout data between design tools of different vendors, all of which operated with proprietary data formats.
It was originally developed by Calma for its layout design software, "Graphic Data System" ("GDS") and "GDS II". Now the format is owned by Cadence Design Systems.
GDS II files are usually the final output product of the IC design cycle and are given to IC foundries for IC fabrication. GDS II files were originally placed on magnetic tapes. This moment was fittingly called tape out though it is not the original root of the term.
Objects contained in a GDS II file are grouped by assigning numeric attributes to them including "layer number", "datatype" or "texttype". While these attributes were designed to correspond to the "layers of material" used in manufacturing an integrated circuit, their meaning rapidly became more abstract to reflect the way that the physical layout is designed.
As of October 2004, many EDA software vendors have begun to support a new format, OASIS, which may replace GDS II.
GDS II utilities
As the GDS II stream format is the de facto standard, it is supported by nearly all EDA software. Beside the commercial vendors there are a plenty of free GDSII utilities [1]. These free tools includes editors [2], viewers [3], utilities to convert the 2D layout data into common 3D formats [4] [5], utilities to convert the binary format to a human readable ASCII format [6] and program libraries [7].
Notes
1. List of free GDSII utilities http://www.layouteditor.net/links
2. LayoutEditor, a free GDSII editor http://www.layouteditor.net
3. "KLayout" is a free GDSII viewer http://www.klayout.de
4. gds2pov easily convert GDSII data into a nicely rendered 3D view. http://www.atchoo.org/gds2pov
5. With GdsViewer tool, any portion of GDSII artwork can be exported to 3D VTK file. The latter can be viewed and manipulated with VTK compatible viewers, e.g. ParaView http://www.gbresearch.com/gdsviewer
6. GDS Utilities can convert binary GDSII files to ASCII representation, http://www.gbresearch.com/gdsutilities
7. Ruby GDSII Library for reading, manipulating, and writing GDSII data in the Ruby programming language http://www.rubyforge.org/projects/gdsii
Layout Versus Schematic (LVS)
The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.
Background
A successful Design rule check (DRC) ensures that the layout conforms to the rules designed/required for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. This is where an LVS check is used.
LVS Check
LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. The software then compares them with the schematic or circuit diagram.
LVS Checking involves following three steps:
1. Extraction: The software program takes a database file containing all the layers drawn to represent the circuit during layout. It then runs the database through many logic operations to determine the semiconductor components represented in the drawing by their layers of construction. It then examines the various drawn metal layers and finds how each of these components connects to others.
2. Reduction: During reduction the software combines the extracted components into series and parallel combinations if possible and generates a netlist representation of the layout database.
3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic. If the two netlists match, then the circuit passes the LVS check. At this point it is said to be "LVS clean."
In most cases the layout will not pass LVS the first time requiring the layout engineer to examine the LVS software's reports and make changes to the layout. Typical errors encountered during LVS include:
1. Shorts: Two or more wires that should not be connected together have been and must be separated.
2. Opens: Wires or components that should be connected are left dangling or only partially connected. These must be connected properly to fix this.
3. Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt MOS device instead of a standard Vt MOS device)
4. Missing Components: An expected component has been left out of the layout.
5. Property Errors: A component is the wrong size compared to the schematic.
LVS Software
Commercial LVS Software
* L-Edit LVS by Tanner EDA
* Calibre by Mentor Graphics
* Quartz LVS by Magma
* Hercules LVS by Synopsys
* Assura, Dracula and PVS by Cadence
Background
A successful Design rule check (DRC) ensures that the layout conforms to the rules designed/required for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. This is where an LVS check is used.
LVS Check
LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. The software then compares them with the schematic or circuit diagram.
LVS Checking involves following three steps:
1. Extraction: The software program takes a database file containing all the layers drawn to represent the circuit during layout. It then runs the database through many logic operations to determine the semiconductor components represented in the drawing by their layers of construction. It then examines the various drawn metal layers and finds how each of these components connects to others.
2. Reduction: During reduction the software combines the extracted components into series and parallel combinations if possible and generates a netlist representation of the layout database.
3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic. If the two netlists match, then the circuit passes the LVS check. At this point it is said to be "LVS clean."
In most cases the layout will not pass LVS the first time requiring the layout engineer to examine the LVS software's reports and make changes to the layout. Typical errors encountered during LVS include:
1. Shorts: Two or more wires that should not be connected together have been and must be separated.
2. Opens: Wires or components that should be connected are left dangling or only partially connected. These must be connected properly to fix this.
3. Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt MOS device instead of a standard Vt MOS device)
4. Missing Components: An expected component has been left out of the layout.
5. Property Errors: A component is the wrong size compared to the schematic.
LVS Software
Commercial LVS Software
* L-Edit LVS by Tanner EDA
* Calibre by Mentor Graphics
* Quartz LVS by Magma
* Hercules LVS by Synopsys
* Assura, Dracula and PVS by Cadence
Subscribe to:
Posts (Atom)